1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for fabricating a semiconductor device which improves short channel effect and increases current driving force.
2. Discussion of the Related Art
A conventional semiconductor device and a method for fabricating the same will be described with reference to the accompanying drawings.
FIG. 1 is a schematic view illustrating a conventional semiconductor device. FIG. 2a to FIG. 2d are sectional views illustrating process steps of a method for fabricating a conventional semiconductor device.
As shown in FIG. 1, a gate oxide film 3, a gate electrode 4, and a gate cap insulating film 5 are stacked on a predetermined region of a semiconductor substrate 1. A sidewall insulating film 9 is formed at both sides of the gate oxide film 3, the gate electrode 4, and the gate cap insulating film 5. A lightly doped drain (LDD) region 8 is formed in the semiconductor substrate 1 at both sides of the gate electrode 4. A second halo region 7 is formed at the same depth as the LDD region 8 to surround the LDD region 8. A source/drain region 10 is formed in the semiconductor substrate 1 at both sides of the sidewall insulating film 9. A first halo region 6 is formed in the semiconductor substrate at both sides of the gate electrode 4. The second halo region 7 has a width wider than that of the first halo region 6 and has a depth lower than that of the first halo region 6. These halo regions 7 and 8 overlap each other at a lower edge portion of the LDD region 8.
The method for fabricating the conventional semiconductor device will be described with reference to FIG. 2a to FIG. 2d.
As shown in FIG. 2a, an active region and a field region are defined in a P type semiconductor substrate 1 to form a field oxide film 2 in the field region. A first oxide film, a polysilicon, and a second oxide film are sequentially deposited on an entire surface of the semiconductor substrate 1 and then removed by anisotropic etching process to form a gate oxide film 3, a gate electrode 4, and a gate cap insulating film 5.
P type impurity ions are tilt implanted into the semiconductor substrate 1 at both sides of the gate electrode 4 at an angle between 7.degree. and 20.degree. to form a first halo region 6.
As shown in FIG. 2b, P type impurity ions are implanted into the semiconductor substrate 1 at both sides of the gate electrode 4 at an angle between 30.degree. and 60.degree. to form a second halo region 7. At this time, the second halo region 7 has a width wider than that of the first halo region 6 and has a depth lower than that of the first halo region 6.
As shown in FIG. 2c, N type lightly doped impurity ions are implanted into the semiconductor substrate 1 at both sides of the gate electrode 4 to form an LDD region 8.
As shown in FIG. 2d, an oxide film is deposited on the entire surface of the semiconductor substrate 1 by chemical vapor deposition (CVD) and etched back to form a sidewall insulating film 9 at both sides of the gate electrode 4. N type heavily doped impurity ions are implanted into the semiconductor substrate 1 using the gate electrode 4 and the sidewall insulating film 9 as masks to form a source/drain region 10.
At this time, the first halo region 6 has almost the same depth as that of the source and drain region 10. The second halo region 7 has almost the same depth as that of the LDD region 8. As a result, short channel effect can be improved.
However, the conventional semiconductor device and the method for fabricating the same have several problems.
In the conventional method for fabricating the semiconductor device, the halo region is formed by two times ion implantation processes to improve threshold voltage and short channel effect as well as to adjust breakdown voltage characteristic. This results in that the depth of the ions implanted becomes lower in high integrated device of submicron or less. As a result, the first halo region and the second halo region overlap each other.
The first halo region requires heavily doped impurity ions to adjust breakdown voltage, as the length of the channel becomes shorter in the high integrated device. This results in that the doping density becomes heavier at the portion where the first halo region and the second halo region overlap each other and that the threshold voltage increases at the portion where the doping density is heavy. As a result, it is difficult to adjust operational characteristic of the device.